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? semiconductor components industries, llc, 2012 november, 2012 ? rev. 9 1 publication order number: NB3H83905C/d NB3H83905C 1.8v/2.5v/3.3v crystal input to 1:6 lvttl/lvcmos clock fanout buffer with oe description the NB3H83905C is a 1.8 v, 2.5 v or 3.3 v v dd core crystal input to 1:6 lvttl/lvcmos fanout buffer with outputs powered by flexible 1.8 v, 2.5 v, or 3.3 v supply v ddo (with v dd v ddo ). the device accepts a fundamental parallel resonant crystal from 3 mhz to 40 mhz or a single ? ended lvcmos clock from up to 100 mhz. two synchronous lvttl/lvcmos enable lines permit independent control over outputs bclk[0:4] and output bclk5; enabling or disabling only when the output is in low state eliminating potential output glitching or runt pulse generation. when unused, leave floating open, pins will default to high state. the 6 outputs drive 50 series or parallel terminated transmission lines. parallel termination should be to 1/2 v cc . series terminated lines can drive 2 loads each, or 12 lines total. fit, form, and function compatible with ics83905 and pi6c10806. features ? six copies of lvttl/lvcmos output clock ? supply operation v dd v ddo : ? 1.8 v 0.2 v, 2.5 v 5% or 3.3 v 5% core v dd ? 1.8 v 0.2 v, 2.5 v 5%, or 3.3 v 5% output v ddo ? crystal oscillator interface ? crystal input frequency range: 3 mhz to 40 mhz ? clock input frequency range: up to 100 mhz ? lvcmos compatible enable inputs ? 5 v tolerant enable inputs ? low output to output skew: 80 ps max ? synchronous output enable ? phase noise floor ? 160 dbc (1 mhz) ? industrial temperature range ? these are pb ? free devices figure 1. simplified block diagram bclk0 bclk1 bclk2 bclk3 bclk4 bclk5 sync sync xtal_in/clk xtal_out c1 c2 enable1 enable2 marking diagrams* *for additional marking information, refer to application note and8002/d. soic ? 16 d suffix case 751b see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information http://onsemi.com tssop ? 16 dt suffix case 948f (*note: microdot may be in either location) qfn20 mn suffix case 485bh 1 16 nb3h 905c alyw 1 16 a = assembly location l = wafer lot yy, y = year ww, w = work week g or = pb ? free package nb3h83905g alyyww 1 16 1 nb3h 83905 alyw 1 20
NB3H83905C http://onsemi.com 2 figure 2. pinout configuration (top view) 1 xtal_out 16 xtal_in/clk 2 enable2 3 gnd 4 bclk0 15 enable1 14 bclk5 13 v ddo soic ? 16/tssop ? 16 5 12 6 7 8 11 10 9 v ddo bclk4 bclk1 gnd bclk2 gnd bclk3 v dd bclk5 v ddo bclk4 gnd gnd gnd gnd bclk0 v ddo bclk1 enable2 xtal_out xtal_in/clk enable1 nc gnd gnd bclk2 v dd bclk3 qfn20 1 2 3 4 5 15 14 13 12 11 10 9 8 7 6 16 17 18 19 20 ep exposed pad table 1. pin description soic ? 16 / tssop ? 16 qfn ? 20 name i/o description 1 19 xtal_out crystal interface oscillator output to drive crystal 2 20 enable 2 lvttl / lvcmos input synchronous enable input for bclk5 output. switches only when high. open default condition high due to an internal pullup resistor to v cc . 3, 7, 11 1, 2, 6, 7, 11, 12 gnd gnd gnd supply pins. all gnd, v dd and v ddo pins must be externally connected to power supply to guarantee proper operation. 4, 6, 8, 10, 12, 14 3, 5, 8, 10, 13, 15 bclk0, 1, 2, 3, 4, 5 lvcmos outputs buffered clock outputs 5, 13 4, 14 v ddo power positive supply voltage for outputs. all gnd, v dd and v ddo pins must be externally connected to power supply to guarantee proper operation. bypass with 0.01 f cap to gnd. 9 9 v dd power positive supply voltage for core. all gnd, v dd and v ddo pins must be externally connected to power supply to guarantee proper operation. bypass with 0.01 f cap to gnd. ? 16 nc no connect 15 17 enable 1 lvttl / lvcmos input synchronous enable input for bclk0/1/2/3/4 output block. switches only when high. open default condition high due to an internal pullup resistor to v cc 16 18 xtal_in/ clk crystal interface oscillator input from crystal. single ended clock input. ? ep ? the exposed pad (ep) on the qfn ? 20 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to gnd on the pc board.
NB3H83905C http://onsemi.com 3 table 2. clock enable function table control inputs outputs enable1* enable2* bclk0:bclk4 bclk5 0 0 low low 0 1 low toggling 1 0 toggling low 1 1 toggling toggling *defaults high when floating open. figure 3. enablex control timing diagram bclk5 bclk0:4 enable2 enable1 the enablex control inputs will synchronously enable or disable the selected output(s). this control detects the falling edge of the internal signal and asserts or de ? asserts the output after 3 clock cycles. when enablex is low, the outputs are disabled to a low state. when enablex is high, the outputs are enabled to toggle. table 3. recommended crystal parameters crystal fundamental at ? cut frequency 10 to 40 mhz load capacitance* 16 ? 20 pf shunt capacitance, c0 7 pf max equivalent series resistance 50 max drive level 1 mw *see application information; crystal input interface for cl loading table 4. attributes (note 1) characteristics value esd protection human body model machine model > 2 kv > 200 v moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index ul ? 94 code v ? 0 a 1/8? 28 to 34 transistor count 213 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
NB3H83905C http://onsemi.com 4 table 5. maximum ratings (note 2) symbol parameter condition 1 condition 1 rating unit v ddx positive power supply gnd = 0 v 4.6 v v i input voltage ?0.5 v i v dd + 0.5 v t a operating temperature range, industrial ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm soic ? 16 soic ? 16 80 55 c/w jc thermal resistance (junction ? to ? case) (note 3) soic ? 16 33 ? 36 c/w ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm tssop ? 16 tssop ? 16 138 108 c/w jc thermal resistance (junction ? to ? case) (note 3) tssop ? 16 33 ? 36 c/w ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm qfn ? 20 qfn ? 20 47 33 c/w jc thermal resistance (junction ? to ? case) (note 3) qfn ? 20 18 c/w t sol wave solder 3 sec @ 248 c 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simu ltaneously. if stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power).
NB3H83905C http://onsemi.com 5 table 6. dc characteristics symbol characteristic min typ max unit v dd = v ddo = 3.135 v to 3.465 v (3.3 v 5%); gnd = 0 v, t a = ? 40 c to +85 c idd core quiescent power supply current (enablex = low) 10 ma iddo output quiescent power supply current (enablex = low) 5 ma v ih input high voltage enablex, xtal_in/clk 2 v dd + 0.3 v v v il input low voltage enablex, xtal_in/clk ? 0.3 0.8 v v oh output high voltage (note 4) 2.6 v v ol output low voltage (note 4) 0.5 v c in input capacitance 4 pf c pd power dissipation capacitance (per output) (note 4) 19 pf r out output impedance (note 4) 7 v dd = v ddo = 2.375 v to 2.625 v (2.5 v 5%); gnd = 0 v, t a = ? 40 c to +85 c idd core quiescent power supply current (enablex = low) 8 ma iddo output quiescent power supply current (enablex = low) 4 ma v ih input high voltage enablex, xtal_in/clk 1.7 v dd + 0.3 v v v il input low voltage enablex, xtal_in/clk ? 0.3 0.7 v v oh output high voltage (i oh = ? 1 ma) output high voltage (note 4) 2.0 1.8 v v ol output low voltage (i ol = 1 ma) output low voltage (note 4) 0.4 0.45 v c in input capacitance 4 pf c pd power dissipation capacitance (per output) (note 4) 18 pf r out output impedance (note 4) 7 v dd = v ddo = 1.6 v to 2.0 v (1.8 v 0.2 v); gnd = 0 v, t a = ? 40 c to +85 c idd core quiescent power supply current (enablex = low) 5 ma iddo output quiescent power supply current (enablex = low) 3 ma v ih input high voltage enablex, xtal_in/clk 0.65*v dd v dd + 0.3 v v v il input low voltage enablex, xtal_in/clk ? 0.3 0.35*v dd v v oh output high voltage (note 4) v ddo ? 0.3 v v ol output low voltage (note 4) 0.35 v c in input capacitance 4 pf c pd power dissipation capacitance (per output) (note 4) 16 pf r out output impedance (note 4) 10 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. parallel terminated 50 to v ddo /2 (see figure 5).
NB3H83905C http://onsemi.com 6 table 6. dc characteristics (continued) symbol unit max typ min characteristic v dd = 3.135 v to 3.465 v (3.3 v 5%); v ddo = 2.375 v to 2.625 v (2.5 v 5%); gnd = 0 v, t a = ? 40 c to +85 c idd core quiescent power supply current (enablex = low) 10 ma iddo output quiescent power supply current (enablex = low) 4 ma v ih input high voltage enablex, xtal_in/clk 2 v dd + 0.3 v v v il input low voltage enablex, xtal_in/clk ? 0.3 0.8 v v oh output high voltage (i oh = ? 1 ma) output high voltage (note 4) 2.0 1.8 v v ol output low voltage (i ol = 1 ma) output low voltage (note 4) 0.4 0.45 v c in input capacitance 4 pf c pd power dissipation capacitance (per output) (note 4) 18 pf r out output impedance (note 4) 7 v dd = 3.135 v to 3.465 v (3.3 v 5%); v ddo = 1.6 v to 2.0 v (1.8 v 0.2 v.); gnd = 0 v, t a = ? 40 c to +85 c idd core quiescent power supply current (enablex = low) 10 ma iddo output quiescent power supply current (enablex = low) 3 ma v ih input high voltage enablex, xtal_in/clk 2 v dd + 0.3 v v v il input low voltage enablex, xtal_in/clk ? 0.3 0.8 v v oh output high voltage (note 4) v ddo ? 0.3 v v ol output low voltage (note 4) 0.35 v c in input capacitance 4 pf c pd power dissipation capacitance (per output) (note 4) 16 pf r out output impedance (note 4) 10 v dd = 2.375 v to 2.625 v (2.5 v 5%); v ddo = 1.6 v to 2.0 v (1.8 v 0.2 v); gnd = 0 v, t a = ? 40 c to +85 c idd core quiescent power supply current (enablex = low) 8 ma iddo output quiescent power supply current (enablex = low) 3 ma v ih input high voltage enablex, xtal_in/clk 1.7 v dd + 0.3 v v v il input low voltage enablex, xtal_in/clk ? 0.3 0.7 v v oh output high voltage (note 4) v ddo ? 0.3 v v ol output low voltage (note 4) 0.35 v c in input capacitance 4 pf c pd power dissipation capacitance (per output) (note 4) 16 pf r out output impedance (note 4) 10 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. parallel terminated 50 to v ddo /2 (see figure 5).
NB3H83905C http://onsemi.com 7 table 7. ac characteristics symbol characteristic min typ max unit v dd = v ddo = 3.135 v to 3.465 v (3.3 v 5%); gnd = 0 v, t a = ? 40 c to +85 c (note 5) f max input frequency crystal 3 40 mhz input frequency clock (xtal_in/clk) dc 100 t en / t dis delay for output enable / disable time enablex to bclkn 4 cycles tskew dc duty cycle skew (see figure 4) 48 52 % tskew o ? o output to output skew within a device (same conditions) 0 50 80 ps noise phase ? noise performance f out = 25 mhz 100 hz off carrier 1 khz off carrier 10 khz off carrier 100 khz off carrier ? 123 ? 142 ? 153 ? 164 dbc/hz tjit( ) rms phase jitter 25 mhz carrier, integration range 12 khz to 20 mhz 25 mhz carrier, integration range 100 hz to 1 mhz 0.08 0.08 ps tr/tf output rise and fall times (20%; 80%) 200 800 ps v dd = v ddo = 2.375 v to 2.625 v (2.5 v 5%); gnd = 0 v, t a = ? 40 c to +85 c (note 5) f max input frequency crystal 3 40 mhz input frequency clock (xtal1) dc 100 t en / t dis delay for output enable / disable time enablex to bclkn 4 cycles tskew dc duty cycle skew (see figure 4) 47 53 % tskew o ? o output to output skew within a device (same conditions) 0 50 80 ps noise phase ? noise performance f out = 25 mhz 100 hz off carrier 1 khz off carrier 10 khz off carrier 100 khz off carrier ? 11 8 ? 137 ? 151 ? 165 dbc/hz tjit( ) rms phase jitter 25 mhz carrier, integration range 12 khz to 20 mhz 25 mhz carrier, integration range 100 hz to 1 mhz 0.13 0.13 ps tr/tf output rise and fall times (20%; 80%) 200 800 ps v dd = v ddo = 1.6 v to 2.0 v (1.8 v 0.2 v); gnd = 0 v, t a = ? 40 c to +85 c (note 5) f max input frequency crystal 3 40 mhz input frequency clock (xtal1) dc 100 t en / t dis delay for output enable / disable time enablex to bclkn 4 cycles tskew dc duty cycle skew (see figure 4) 47 53 % tskew o ? o output to output skew within a device (same conditions) 0 50 80 ps noise phase ? noise performance f out = 25 mhz 100 hz off carrier 1 khz off carrier 10 khz off carrier 100 khz off carrier ? 129 ? 145 ? 147 ? 157 dbc/hz tjit( ) rms phase jitter 25 mhz carrier, integration range 12 khz to 20 mhz 25 mhz carrier, integration range 100 hz to 1 mhz 0.27 0.27 ps tr/tf output rise and fall times (20%; 80%) 200 900 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. crystal inputs f max . outputs loaded with 50 to v ddo /2. clock (lvcmos levels at xtal1 input) 50% duty cycle. see figures 4 and 7. see application information; crystal input interface for cl loading.
NB3H83905C http://onsemi.com 8 table 7. ac characteristics (continued) symbol unit max typ min characteristic v dd = 3.135 v to 3.465 v (3.3 v 5%); v ddo = 2.375 v to 2.625 v (2.5 v 5%); gnd = 0 v, t a = ? 40 c to +85 c (note 5) f max input frequency crystal 3 40 mhz input frequency clock (xtal_in/clk) dc 100 t en / t dis delay for output enable / disable time enablex to bclkn 4 cycles tskew dc duty cycle skew (see figure 4) 48 52 % tskew o ? o output to output skew within a device (same conditions) 0 50 80 ps noise phase ? noise performance f out = 25 mhz 100 hz off carrier 1 khz off carrier 10 khz off carrier 100 khz off carrier ? 129 ? 145 ? 147 ? 157 dbc/hz tjit( ) rms phase jitter 25 mhz carrier, integration range 12 khz to 20 mhz 25 mhz carrier, integration range 100 hz to 1 mhz 0.14 0.14 ps tr/tf output rise and fall times (20%; 80%) 200 800 ps v dd = 3.135 v to 3.465 v (3.3 v 5%); v ddo = 1.6 v to 2.0 v (1.8 v 0.2 v); gnd = 0 v, t a = ? 40 c to +85 c (note 5) f max input frequency crystal 3 40 mhz input frequency clock (xtal1) dc 100 t en / t dis delay for output enable / disable time enablex to bclkn 4 cycles tskew dc duty cycle skew (see figure 4) 48 52 % tskew o ? o output to output skew within a device (same conditions) 0 50 80 ps noise phase ? noise performance f out = 25 mhz 100 hz off carrier 1 khz off carrier 10 khz off carrier 100 khz off carrier ? 129 ? 145 ? 147 ? 157 dbc/hz tjit( ) rms phase jitter 25 mhz carrier, integration range 12 khz to 20 mhz 25 mhz carrier, integration range 100 hz to 1 mhz 0.18 0.18 ps tr/tf output rise and fall times (20%; 80%) 200 900 ps v dd = 2.375 v to 2.625 v (2.5 v 5%); v ddo = 1.6 v to 2.0 v (1.8 v 0.2 v); gnd = 0 v, t a = ? 40 c to +85 c (note 5) f max input frequency crystal 3 40 mhz input frequency clock (xtal1) dc 100 t en / t dis delay for output enable / disable time enablex to bclkn 4 cycles tskew dc duty cycle skew (see figure 4) 47 53 % tskew o ? o output to output skew within a device (same conditions) 0 50 80 ps noise phase ? noise performance f out = 25 mhz/ 100 hz off carrier 1 khz off carrier 10 khz off carrier 100 khz off carrier ? 129 ? 145 ? 147 ? 157 dbc/hz tjit( ) rms phase jitter 25 mhz carrier, integration range 12 khz to 20 mhz 25 mhz carrier, integration range 100 hz to 1 mhz 0.19 0.19 ps tr/tf output rise and fall times (20%; 80%) 200 900 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. crystal inputs f max . outputs loaded with 50 to v ddo /2. clock (lvcmos levels at xtal1 input) 50% duty cycle. see figures 4 and 7. see application information; crystal input interface for cl loading.
NB3H83905C http://onsemi.com 9 figure 4. ac reference measurement t r t skew t f 80% 20% bclkx t pw t p v ddo 2 t skewdc % t pw t p 100% v ddo 2 v ddo 2 v ddo 2 v ddo 2 v ddo 2 v ddo 2 bclkx bclky bclkx o ? o t skew o ? o figure 5. typical phase noise plot of the NB3H83905C operating at 25 mhz v dd = v ddo = 3.3 v
NB3H83905C http://onsemi.com 10 figure 6. typical phase noise plot of the NB3H83905C operating at 25 mhz v dd = v ddo = 2.5 v bclkx in z o = 50 NB3H83905C scope 50 v dd v ddo dut gnd figure 7. typical device evaluation and termination setup ? see table 8 gnd table 8. test supply setup. v ddo supply may be centered on 0.0 v (scope gnd) to permit direct connection into ?50 to gnd? scope module. v dd supply tracks dut gnd pin spec condition: test setup v dd : test setup v ddo : test setup dut gnd: v dd = v ddo = 3.135 v to 3.465 v (3.3 v 5%) 1.56 to 1.73 v 1.56 to 1.73 v ? 1.56 to ? 1.73 v v dd = v ddo = 2.375 v to 2.625 v (2.5 v 5%) 1.1875 to 1.3125 v 1.1875 to 1.3125 v ? 1.1875 to ? 1.3125 v v dd = v ddo = 1.6 v to 2.0 v (1.8 v 0.2 v) 0.8 to 1.0 v 0.8 to 1.0 v ? 0.8 to ? 1.0 v v dd = 3.135 v to 3.465 v (3.3 v 5%); v ddo = 2.375 v to 2.625 v (2.5 v 5%) 1.955 to 2.1525 v 1.1875 to 1.3125 v ? 1.1875 to ? 1.3125 v v dd = 3.135 v to 3.465 v (3.3 v 5%); v ddo = 1.6 v to 2.0 v (1.8 v 0.2 v) 2.335 to 2.465 v 0.8 to 1.0 v ? 0.8 to ? 1.0 v v dd = 2.375 v to 2.625 v (2.5 v 5%); v ddo = 1.6 v to 2.0 v (1.8 v 0.2 v) 1.575 to 1.625 v 0.8 to 1.0 v ? 0.8 to ? 1.0 v
NB3H83905C http://onsemi.com 11 application information crystal input interface figure 8 shows the NB3H83905C device crystal oscillator interface using a typical parallel resonant crystal. a parallel crystal with loading capacitance c l = 18 pf would use c1 = 32 pf and c2 = 32 pf as nominal values, assuming 4 pf of stray cap per line. the frequency accuracy and duty cycle skew can be fine tuned by adjusting the c1 and c2 values. for example, increasing the c1 and c2 values will reduce the operational frequency. note r1 is optional and may be 0 . figure 8. NB3H83905C crystal oscillator interface * r1 is optional 32 pf 32 pf c1 c2 NB3H83905C xtal_in/clk xtal_out r1* x1 18 pf parallel resonant crystal termination NB3H83905C device output series termination may be used by locating a 28 series resistor at the driver pin as shown in figure 9. alternatively, a thevenin parallel termination may be used by locating a 100 pullup resistor to v dd and a 100 pullup resistor to gnd at the receiver pin, instead of an rs source termination resistor, figure 10. unused input and output pins all lvcmos control pins have internal pull ? ups or pull ? downs; additional external resistors are not required (optionally 1 k resistors may be used). all unused lvcmos outputs can be left floating with no trace attached. bypass the v dd and v ddo supply pins should be bypassed with both a 10 f and a 0.1 f cap from supply pins to gnd. figure 9. series termination figure 10. optional thevenin termination rseries = 28 bclkx lvcmos r = 100 r = 100 lvcmos bclkx ordering information device package shipping ? NB3H83905Cdg soic ? 16 (pb
free) 48 units / rail NB3H83905Cdr2g soic ? 16 (pb
free) 2500 units / tape & reel NB3H83905Cdtg tssop ? 16 (pb
free) 96 units /rail NB3H83905Cdtr2g tssop ? 16 (pb
free) 2500 units / tape & reel NB3H83905Cmng qfn ? 20 (pb ? free) 92 units / rail NB3H83905Cmntxg qfn ? 20 pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB3H83905C http://onsemi.com 12 package dimensions soic ? 16 case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
NB3H83905C http://onsemi.com 13 package dimensions tssop ? 16 case 948f issue b ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
NB3H83905C http://onsemi.com 14 package dimensions qfn20 4x4, 0.5p case 485bh issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? ???? a d e b c 0.15 pin one reference top view side view bottom view a k d2 e2 c c 0.15 c 0.10 c 0.08 a1 seating plane e 20x note 3 b 20x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 ??? 0.05 b 0.20 0.30 d 4.00 bsc d2 2.60 2.80 e 4.00 bsc e2 2.60 2.80 e 0.50 bsc k 0.20 ??? l 0.35 0.45 6 11 16 20x 0.50 pitch 4.30 0.60 4.30 dimensions: millimeters 0.35 20x 1 l a3 0.20 ref mounting footprint* note 4 a3 detail b 2.80 2.80 1 package outline detail a l1 detail a l alternate terminal constructions l 0.00 0.15 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NB3H83905C/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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